In the manufacturing of integrated circuits, circuit devices such as transistors are first formed on a semiconductor substrate. An interconnect structure including metal lines and vias is then formed to connect the circuit devices as functional circuits. To form the interconnect structure, a plurality of dielectric layers are formed, and the metal lines and vias are formed in the dielectric layers.
As the semiconductor industry introduces new generations of Integrated Circuits (IC) having higher performance and more functionality, the density of the elements forming the ICs increases, while the dimensions, sizes, and spacing between components or elements are reduced. In the past, such reductions were limited only by the ability to define the structures photo-lithographically, and device geometries having smaller dimensions create new limiting factors. For example, for any two adjacent conductive features, as the distance between the conductive features decreases, the resulting capacitance (a function of the dielectric constant (k value) of the insulating material divided by the distance between the conductive features) increases. This increased capacitance results in increased power consumption and increased resistive-capacitive (RC) delay. Therefore, the continual improvement in semiconductor IC performance and functionality is dependent upon developing materials with low k values.
The reduction in the k value, however, conflicts with the requirements of other devices such as capacitors. The capacitance of a capacitor is proportional to the k value of the capacitor insulator between the capacitor plates. Accordingly, with the reduction in the k value, it is difficult to form capacitors with high capacitance values.